1. Field of the Invention
The present invention relates to an asynchronous absorption circuit in a system LSI that has a plurality of clock domains and in which operating frequencies of the clock domains vary depending on the application, or an asynchronous absorption circuit between two LSIs in a set system including a plurality of system LSIs.
2. Description of the Related Art
A system LSI has blocks having asynchronous frequency domains or a set system has a plurality of system LSIs having asynchronous frequency domains. There is a known technique in which a signal is transferred via an asynchronous absorption circuit capable of stable asynchronous absorption by expanding a pulse signal having a clock of a preceding stage at an asynchronous absorption interface.
According to a conventional technique, a frequency dividing means is provided upstream of a pulse generating circuit so that a signal can be reliably transferred between circuits that operate with different clock frequencies in a network display, for example (see Japanese Unexamined Patent Application Publication No. 2000-115147).
FIG. 1 shows an exemplary conventional asynchronous absorption circuit including a frequency dividing means. In FIGS. 1, 10, 11 and 12 indicate first to third flip-flops, 13 indicates a three-input OR gate, and 14, 15 and 16 indicate fourth to sixth flip-flops, SIG indicates an input signal, CLKA indicates a clock signal of a preceding stage (hereinafter referred to as a preceding clock signal), and CLKB indicates a clock signal of a succeeding stage (hereinafter referred to as a succeeding clock signal). The first to fourth flip-flops 10, 11, 12 and 14 receive the preceding clock signal CLKA. The fifth and sixth flip-flops 15 and 16 receive the succeeding clock signal CLKB. The input signal SIG is a pulse signal that has a HIGH period whose length corresponds to one cycle of the preceding clock signal CLKA.
For example, the preceding clock signal CLKA has a frequency of 67.5 MHz, and the succeeding clock signal CLKB has a frequency of 28.93 MHz. The three-input OR gate 13 receives an output signal SIGA of the first flip-flop 10, an output signal SIGB of the second flip-flop 11, and an output signal SIGC of the third flip-flop 12, and supplies a frequency-divided signal SIGL to the fourth flip-flop 14. Specifically, the frequency-divided signal SIGL is a signal that is obtained by expanding the HIGH period (one cycle of CLKA) of the input signal SIG by a factor of three.
An output signal SIGD of the fourth flip-flop 14 is input to the fifth flip-flop 15 that operates in synchronization with the succeeding clock signal CLKB. An output signal SIGDA of the fifth flip-flop 15 is input to the sixth flip-flop 16 that operates in synchronization with the succeeding clock signal CLKB. SIGDB indicates an output signal of the sixth flip-flop 16.